Computer Architecture

Chapter 1 Part 1 [RDW]

Chapter 1 Part 2 [RDW]

Chapter 1 Part 3 [RDW]

Chapter 1 Part 4 [RDW]

Chapter 1 Part 5 [RDW]

Computer Architecture Models & Performance - Class Recording Part 1 [PBK]

Computer Architecture Models & Performance - Class Recording Part 2 [PBK]

Practice Problem 1 (Chapter 1) [PBK]

Practice Problem 2 (Chapter 1) [PBK]

Practice Problem 3 (Chapter 1) [PBK]

Practice Problem 4 (Chapter 1) [PBK]

Chapter 1 Part 3 [AFQ]

Chapter 1 Part 2 [AFQ]

Chapter 1 Part 1 [AFQ]

Chapter 2 Part 1 [RDW]

Chapter 2 Part 2 [RDW]

Chapter 2 Part 3 [RDW]

Chapter 2 Part 4 [RDW]

Chapter 2 Part 5 [RDW]

Chapter 2 Part 6 [RDW]

Chapter 2 Part 7 [RDW]

Intro to RISC-V [PBK]

RISC-V Register Functionalities [PBK]

Operand, Register Operand [PBK]

Memory Operand 1 [PBK]

Memory Operand 2 [PBK]

Load, Store Instruction Syntax Explanation [PBK]

Immediate Operands 1 [PBK]

Immediate Operand 2 [PBK]

Sign Extensions [PBK]

Desire to Keep All Instructions Length Same vs Format Same [PBK]

R-Type Instruction Format [PBK]

I-Type Instruction Format [PBK]

S-Type Instruction Format [PBK]

SLLI, SRLI [PBK]

AND [PBK]

OR, NOT, Buffer (XOR) [PBK]

Practice Problem 1 (Chapter 2) [PBK]

Practice Problem 2 (Chapter 2) [PBK]

Decision Making / If-Else / Branching [PBK]

Loop [PBK]

Forming a 32-bit Immediate using LUI [PBK]

SB-Type Instruction Format [PBK]

UJ-Type Instruction Format [PBK]

Procedure Calling [PBK]

Leaf Example 1 [PBK]

Procedure Calling [AFQ]

UJ, SB and U-Type Format [LRK]

S-Format, Shift Left/Right, Conditional Branching, Loop [LRK]

Long Multiplication Hardware Explanation [PBK]

Long Multiplication Logic and Example (Unsigned) [PBK]

Intro to IEEE-754 Floating Point Representation [PBK]

Characteristics of a Normalized Number [PBK]

How to Normalize a Number with Example [PBK]

IEEE-754 Floating Point Representation Syntax Explanation 1 [PBK]

IEEE-754 Floating Point Representation Syntax Explanation 2 [PBK]

Bias, Biased Exponent Calculation with Example [PBK]

Decimal to Floating Point Conversion with Example [PBK]

Decimal to Floating Point Conversion Example 2 (Customized Field Sizes) [PBK]

Floating Point to Decimal Conversion with Example [PBK]

Floating Point Addition/Subtraction with Example [PBK]

Floating Point Multiplication with Example [PBK]

Overflow/Underflow Detection with Example [PBK]

LUI Recap & Intro to Computer Arithmetic [AFQ]

Floating Point Instruction [AFQ]

Chapter 3 Part 2 [AFQ]

Chapter 3 Part 1 [AFQ]

Floating Point Code [LRK]

Chapter 3 Introduction [LRK]

Chapter 3 - Practice Problem 14 [LRK]

Chapter 3 - Practice Problem 10 (i) [LRK]

Intro to Chapter 4 [PBK]

Basic Steps of Instruction Execution [PBK]

Simulation of the Basic Steps of Instruction Execution [PBK]

Explanation of Register File [PBK]

Explanation of ALU [PBK]

Explanation of Data Memory and Immediate Generation Unit [PBK]

Basics of R-Type Instruction [PBK]

Basics of Load/Store [PBK]

Basics of Branch Instruction [PBK]

Explanation of Control Unit and ALU Control [PBK]

Datapath for Instruction Fetch [PBK]

Datapath for R-Type Instruction [PBK]

Datapath for Load Instruction [PBK]

Datapath for Store Instruction [PBK]

Datapath for Branch Instruction [PBK]

Full Datapath Explanation [PBK]

Full Datapath Review for Load Instruction [PBK]

Pipeline Basics [PBK]

Clock Period Calculation for Single-Cycle and Pipelined Datapath [PBK]

Structural Hazard Explanation [PBK]

Data Hazard Explanation [PBK]

Resolving Data Hazard using Stalling with Example [PBK]

Resolving Data Hazard using Forwarding [PBK]

Resolving Data Hazard using Stall + Forward Example [PBK]

Resolving Data Hazard using Stall + Forward + Code Scheduling Example [PBK]

Data Hazard - Solved Examples [AFQ]

Code Scheduling, Branching/Jumping Hazards [LRK]

Hazard (Structural and Data Hazard) [LRK]

Pipeline Introduction and Performance [LRK]

Background, Exploring Temporal & Spatial Locality, Why We Need Memory Hierarchy [PBK]

Exploring Memory Hierarchy, SRAM vs DRAM, Different Levels of Cache [PBK]

SRAM vs DRAM Continued [PBK]

Block, Cache Hit-Miss, Hit and Miss Ratio, Hit Time, Miss Penalty Explanation [PBK]

Direct Mapped Cache Explanation [PBK]

Address Subdivision: Tag, Index, Offset Bits with Valid Bit and Examples [PBK]

Index Bits Calculation: Given Block Address or Memory Address with Example [PBK]

Offset Bits in Action - Simulation [PBK]

Direct Mapped Cache Simulation with Hit Ratio and Miss Ratio [PBK]

How to Determine if an Access is a Cache Hit or Cache Miss [PBK]

Block Size Considerations: Larger Blocks Pros and Cons [PBK]

What Happens When a Cache Miss? [PBK]

Cache Hit on Write Operation: Write-Through and Write-Back Policy [PBK]

Cache Miss on Write Operation: Write Allocation and No-Write Allocation [PBK]

Cache Write Policy [AFQ]

Direct Mapped Cache [AFQ]

Memory Hierarchy Chapter 5 Part 1 [LRK]

Memory (Read/Write Miss Handling) Chapter 5 Part 2 [LRK]