OR Gate using NOR Gate | Universal Gate | NOR Realization | Digital Logic Design [DZK]

Any Base to Decimal Conversion | Digital Logic Design [DZK]

Decimal to Base-R (Any Base) Conversion | Digital Logic Design [DZK]

Binary to Octal or Hexadecimal and Vice Versa | Digital Logic Design [DZK]

Binary to Octal or Hexadecimal Another Example | Digital Logic Design [DZK]

Base-R (Any Base) Addition | Digital Logic Design [DZK]

Base-R (Any Base) Subtraction | Digital Logic Design [DZK]

Base-R (Any Base) Multiplication | Digital Logic Design [DZK]

Base-R (Any Base) Division | Digital Logic Design [DZK]

CSE260 Summer25 Sec 08-09: Lecture 1 (First Half) [PBK]

CSE260 Summer25 Sec 08-09: Lecture 1 (Second Half) [PBK]

Example - 1: Base-R Addition (Whole Number) [PBK]

Example - 2: Base-R Addition (with Radix point) [PBK]

Example - 3: Base-R Subtraction (Whole Number) [PBK]

Example - 4: Base-R Subtraction (with Radix Point) [PBK]

Example - 5: Base-R Multiplication (with Radix Point) [PBK]

Example - 6: Base-R Division (Whole Number) [PBK]

Number System Basics & Calculations [SUE]

SPRING23 CSE260 Week 1&2 Review

Sign & Magnitude System | Digital Logic Design [DZK]

Decimal to BCD/Excess 3 | Digital Logic Design [DZK]

Unsigned & Signed Number (Basic Intro) | Digital Logic Design [DZK]

Represent a Negative Decimal Number using 2's Complement | Digital Logic Design [DZK]

2's Complement Addition/Subtraction (Example 1) | Digital Logic Design [DZK]

2's Complement Addition Subtraction (Example 2) | Digital Logic Design [DZK]

2's Complement Addition Subtraction (Example 3) | Digital Logic Design [DZK]

CSE260 Spring26: Lecture 2 [PBK]

Signed & Unsigned Numbers [SUE]

Introduction to Logic Gates | English [DZK]

Introduction to Logic Gates | Bangla [DZK]

Boolean Simplification (Different Examples) | Digital Logic Design [DZK]

Duality & Complement of a Function | Digital Logic Design [DZK]

NAND as Universal Gate | English [DZK]

NAND as Universal Gate | Bangla [DZK]

NOR as Universal Gate | Bangla [DZK]

NOR as Universal Gate | English [DZK]

NOT Gate using NAND Gate | Universal Gate | NAND Realization | Digital Logic Design [DZK]

AND Gate using NAND Gate | Universal Gate | NAND Realization | Digital Logic Design [DZK]

OR Gate using NAND Gate | Universal Gate | NAND Realization | Digital Logic Design [DZK]

NOT Gate using NOR Gate | Universal Gate | NOR Realization | Digital Logic Design [DZK]

AND Gate using NOR Gate | Universal Gate | NOR Realization | Digital Logic Design [DZK]

Implement a Function using NAND Gate | Universal Gate | NAND Realization | Digital Logic Design [DZK]

Implement a Function using NOR Gate | Universal Gate | NOR Realization | Digital Logic Design [DZK]

Boolean Simplification - Complex Example 1 | Digital Logic Design [DZK]

Boolean Simplification - Complex Example 2 | Digital Logic Design [DZK]

Boolean Simplification - Complex Example 3 | Digital Logic Design [DZK]

CSE260 Spring26: Lecture 3 Part - 1 [PBK]

CSE260 Spring26: Lecture 3 Part - 2 [PBK]

SPRING23 CSE260 CIRCUIT BUILDING WITH UNIVERSAL GATES

CSE260 Universal Gate SOP POS

CSE260 Universal Gate SOP POS (S12)

CSE260 Boolean Algebra

SPRING23 CSE260 Week 3&4 Review

Min Terms & Max Terms | Digital Logic Design [DZK]

Min Terms & Max Terms from a Truth Table | Digital Logic Design [DZK]

Complement Minterm to get Maxterm | Digital Logic Design [DZK]

Canonical SOP of a function | Digital Logic Design [DZK]

Canonical POS of a function | Digital Logic Design [DZK]

Canonical SOP & POS (Another Example) | Digital Logic Design [DZK]

Introduction to Karnaugh Map (K-Map) || How to build K-Maps [DZK]

2 Variable K-Maps || K-Map Tutorial [DZK]

K Map Folding Concept || K-Map Tutorial [DZK]

3 Variable K-Maps || K-Map Tutorial [DZK]

4 Variable K-Maps || K-Map Tutorial [DZK]

Why don't we use K-maps for 5,6,7... variables? [DZK]

K Map with Don't Cares || K-map Tutorial [DZK]

Scenario Based K-Map (Sample Problem - 1) | K-Map | Digital Logic Design [DZK]

Scenario Based K-Map (Sample Problem - 2) | K-Map | Digital Logic Design [DZK]

Scenario Based K-Map (Sample Problem - 3) | K-Map | Digital Logic Design [DZK]

Introduction to Tabulation Method | English [DZK]

Introduction to Tabulation Method | Bangla [DZK]

Tabulation Method (without Don't Cares) | English [DZK]

Tabulation Method (without Don't Cares) | Bangla [DZK]

Tabulation Method (with Don't Cares) | English [DZK]

Tabulation Method (with Don't Cares) | Bangla [DZK]

Tabulation Method (Quine-McClusky) | Example Problem [DZK]

K-Map Basics [PBK]

Scenario Based K-Map with Don't care [PBK]

K-Map [SUE]

K map Application s12

K map Application s1

CSE260 s12 Tabulation

CSE260 s12 Kmap

CSE260 s1 Tabulation

CSE260 s1 Kmap

Half Adder | Combinational Circuit | Digital Logic Design [DZK]

Full Adder | Combinational Circuit | Digital Logic Design [DZK]

4 Bit Binary Parallel Adder using Full Adders | Digital Logic Design [DZK]

4 Bit Binary Parallel Adder cum Subtractor | Digital Logic Design [DZK]

BCD to Excess 5 Code Converter using 4 Bit Parallel Adder | Digital Logic Design [DZK]

BCD to Excess 10 Code Converter using 4 Bit Parallel Adder | Digital Logic Design [DZK]

Cascading Adders | Voting System Example | Applications of Adders | Digital Logic Design [DZK]

Comparator Circuit (Part-1) | Magnitude Comparator | Digital Logic Design [DZK]

Comparator Circuit (Part-2) | Magnitude Comparator | Digital Logic Design [DZK]

Comparator Circuit (Part-3) | Magnitude Comparator | Digital Logic Design [DZK]

How to build A=2B with Comparator Circuit | Digital Logic Design [DZK]

How to build A=3+2 with Comparator Circuit | Digital Logic Design [DZK]

How to build A=3-2 with Comparator Circuit | Digital Logic Design [DZK]

Implement A+B if Both Numbers are Greater than or Equal to 8 [DZK]

Implement A - B if B is divisible by 12 [DZK]

Implement A+B if A is divisible by 8 and B is Greater than or Equal to 8 [DZK]

Lecture 6: Basics of H A, F A, Parallel Adder & Applications [PBK]

Lecture 6: Application of N-Bit P.A. Continued [PBK]

CSE260 1 Comparator

CSE260 S12 ADDERS

CSE260 ADDERS APPLICATION

CSE260 S1 ADDERS

CSE260 12 Comparator

Introduction to Decoder | Digital Logic Design [DZK]

Introduction to Demultiplexer (Demux) | Digital Logic Design [DZK]

Introduction to Multiplexer (MUX) | Digital Logic Design [DZK]

How to Build 4x16 Decoder using 3x8 Decoder | Digital Logic Design [DZK]

How to Implement a Boolean Function using Decoder (Example 1) | Digital Logic Design [DZK]

How to Implement a Boolean Function using Decoder (Example 2) | Digital Logic Design [DZK]

How to Implement a 8:1 MUX using 4:1 and 2:1 MUX (Method 1) | Digital Logic Design [DZK]

How to Implement a 8:1 MUX using 4:1 and 2:1 MUX (Method 2) | Digital Logic Design [DZK]

Introduction to Encoder | Digital Logic Design [DZK]

Priority Encoder (Based upon MSB) | Digital Logic Design [DZK]

How to Build AND Gate using 4 to 1 MUX [DZK]

How to Build OR Gate using 4 to 1 MUX [DZK]

How to Implement a Boolean Function using 8 to 1 MUX (Example 1) | Digital Logic Design [DZK]

How to Build NOT Gate using 4 to 1 MUX | Digital Logic Design [DZK]

How to Implement a Boolean Function using 4 to 1 MUX (Example 2) | Digital Logic Design [DZK]

How to Implement a Boolean Function using 8 to 1 MUX (Example 2) | Digital Logic Design [DZK]

How to Implement a Boolean Function using 4 to 1 MUX (Example 1) | Digital Logic Design [DZK]

How to implement a BCD to Excess 3 Code Converter using Decoder & Encoder [DZK]

How to implement a Full Adder using Decoder & Encoder [DZK]

How to Implement a Boolean Function using Both 4 to 1 MUX and 2 to 1 MUX | Digital Logic Design [DZK]

Design a 2 bit Parallel Adder using Encoder and Decoder as internal Circuit [DZK]

Design a 7 Person Voting System using Encoder and Decoder as Full Adders [DZK]

Encoder-Decoder-Mux-Demux [SUE]

CSE260 1 MSI Circuits

CSE260 1 MSI Circuits Applications

CSE260 1 MSI applications continued

CSE260 12 MSI Circuits

CSE260 12 MSI Circuits Applications

CSE260 12 MSI applications continued

SR Latch | Truth Table | Build SR Latch using NAND Gate [DZK]

SR Flip Flop | SR Flip Flop Truth Table | Build SR FF using SR Latch [DZK]

SR Flip Flop Characteristic Table & Excitation Table [DZK]

D Flip Flop | Truth Table | Characteristic Table | Excitation Table [DZK]

JK Flip Flop | Truth Table | Characteristic Table | Excitation Table [DZK]

T Flip Flop | Truth Table | Characteristic Table | Excitation Table [DZK]

SR Latch Timing Diagram - Positive Level [DZK]

JK Flip Flop Timing Diagram - Positive Edge [DZK]

JK Flip Flop Timing Diagram - Negative Edge [DZK]

Timing Diagram from a Circuit Diagram [D and T FF] [DZK]

SR Latch Timing Diagram - Negative Level [DZK]

Timing Diagram from a Circuit Diagram Containing JK and T Flip Flop [DZK]

S-R Latch Explanation [PBK]

S-R Flip Flop Explanation [PBK]

D Flip Flop Explanation [PBK]

J-K Flip Flop Explanation [PBK]

T Flip Flop Explanation [PBK]

Timing Diagram [PBK]

Introduction to flipflops SR&JK flipflops

CSE260 s12 flip flop

CSE260 s1 flip flop

CSE260 12 FLIP FLOP EXCITATION TABLE

CSE260 1 FLIP FLOP EXCITATION TABLE

Design 2 bit Synchronous UP Counter [DZK]

Design 3 bit and 4 bit Synchronous UP Counter [DZK]

State Diagram to Circuit Diagram - 1 | Sequential Circuit Analysis [DZK]

State Diagram to Circuit Diagram - 2 | Sequential Circuit Analysis [DZK]

Circuit Diagram to State Diagram | Sequential Circuit Analysis [DZK]

3 Bit Synchronous Up-Down Counter [DZK]

Counter Practice Problem - 1 | Counter Applications [DZK]

Counter Practice Problem - 2 | Text Based Problem [DZK]

Circuit Diagram to State Diagram Using 3 Different Flip Flops [DZK]

CSE260 F25: S07A-07B; Sequential Circuit - Counter [PBK]

Circuit Diagram to State Diagram [PBK]

State Diagram to Circuit Diagram [PBK]

2 bit and 3 bit Counter Design [PBK]

3 bit UP-Down Counter Design [PBK]

Counter Practice - 1 [PBK]

Counter Practice - 2 [PBK]

Sequential Circuit Analysis [SUE]

CSE260 Sequential Circuit Application

CSE260 Sequential Circuit Application parallel data transfer system

Memory Unit Basic Theory | Block Diagram of Memory Unit [DZK]

Memory Unit Math [DZK]

Logic construction of a 4x3 RAM (with decoder and OR gates) [DZK]

Exploring a Memory Unit - Read & Write Operations [PBK]

What are the requirements to design a 1024 X 16 bit memory [PBK]

Memory Capacity Calculation Example [PBK]

Exploring a Binary Cell (Block Diagram) [PBK]

Designing a 4 X 3 RAM [PBK]

Designing a 2 X 3 RAM with a Read and Write tracing [PBK]

Memory [SUE]

SPRING23 CSE260 MEMORY PART 1

SPRING23 CSE260 5 MEMORY 2

SPRING23 CSE260 6 MEMORY 2

CSE260 FALL23 S01 LAB-5 (part-1) [PBK]

CSE260 FALL23 S01 LAB-5 (part-2) [PBK]

CSE260 FALL23 S04 LAB-6 [PBK]

CSE260 FALL23 S01 LAB-7 [PBK]

CSE260 FALL23 S04 LAB-8 [PBK]

CSE260 FALL23 S01 LAB-8 [PBK]

CSE260 Lab Final Sample Question - 1 - Solve [PBK]

CSE260 Lab Final Sample Question - 2 - Solve [PBK]